Implementing a Multi-Domain System
Tanner EDA provides an integrated, top-down design flow for IoT design that supports all these design domains.
Learn more about key solutions that the Tanner design...
UVM – ‘Stop Hitting Your Brother’ – Coding Guidelines
This paper describes situations where UVM provides multiple ways to solve a problem, explains the issues with certain approaches, recommends solutions, and describes the...
PCIe Simulation Speed-Up Using Mentor QVIP with PLDA PCIe Controller for DMA Applications
The flexibility of Questa VIP was key to creating custom testbenches from scratch that can dynamically adapt to different IP topologies and configurations, mixing PCIe...
Multi-Mode Clock Domain Crossing Verification Enables Analysis Efficiency and Accuracy
Modal CDC analysis configures the design as a set of operational modes and runs CDC analysis on each modal version of the design. Before the modal analysis flow was adopted,...
Coverage Driven Verification of NVMe Using Questa VIP
It also explores how QVIP is used for the verification of NVMe using functional coverage and what things are covered as part of the NVMe QVIP test plan.
Verification...
Fabless Challenges of Integrating Complex Silicon into the IC Package, Even the System PCB
Learn what’s required to build a true, multi-substrate flow for emerging HDAP design requirements.
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