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Designing at the C++ or SystemC-level with a fast path to highest QofR (performance, area and power) for both FPGA and ASIC. Catapult’s ecosystem is more than just “C to RTL”, with HLS-aware code and functional coverage similar to System Verilog, and formal equivalence checking, enabling competitive differentiation and accelerated time-to-market. Having a complete low-power methodology from block to SoC whether starting from C or RTL with PowerPro is also critical in emerging ultra-low-power sensitive markets. This resource will help you find key sessions-panels at DAC from researchers, customers, and our expert technologists; and various resources detailing the recent innovations in HLS, Verification, and RTL Low-Power since DAC 2019. |
